As you may have read in the first part of this series, Soitec (the industry’s leading supplier of SOI wafers) says its 200mm RF-SOI wafers have been used to produce over 20 billion chips, and the company is now in high-volume manufacturing of a 300mm version of its wildly successful RFeSI line (see press release here).
So far it’s been all about RF front-end module – aka FEM – chips that handle the back-and-forth of signals between the transceiver and the antenna, originally in 2G and 3G phones. For 4G/LTE-A (and 5G when that hits), there were new wafer innovations – and now 300mm wafers.
The newest RF-SOI wafers, Soitec’s RFeSI90 series (available in both 200mm and 300mm diameters), offer higher levels of performance such as better uniformity, which chip designers need to achieve greater control of transistor matching in analog designs. Plus with the new wafers designers can use thinner transistors and additional process options to improve RonCoff performance, the figure of merit that’s used to rate the performance of an RF switch. For Soitec customers (and really, anyone doing FEMs these days is a customer), all these advances plus the large supply of 200mm and 300mm wafers means that they can expand their production capacities for RF-SOI devices and produce more highly integrated ICs.
GlobalFoundries, for example, sang the praises of 300mm wafers for RF-SOI at a recent SOI Consortium forum in Tokyo. Here’s a slide from Peter Rabbeni’s talk, (he’s GloFo’s Sr. Director RF Product Marketing and Biz Dev), RFSOI: Defining the RF-Digital Boundary for 5G (you can get the full presentation here):
As you see in the slide above, RF-SOI champion Peregrine Semiconductor introduced the industry’s first 300mm RF-SOI technology – that was back in July 2015. Dubbed UltraCMOS® 11, it’s built on GlobalFoundries’ 130 nm 300mm RF technology platform (read about it here).
Looking forward, GF’s Rabbeni noted, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results. SOI holds great promise in delivering on the key requirements of 5G systems.”
Also at the Tokyo event, Kenji Tateiwa, General Manager of R&D Strategic Planning for TPSCo (that’s TowerJazz/Panasonic), gave a great presentation on 300mm RFSOI Development toward IoT Era. 300mm RF-SOI, he noted, “has room to run.”
For Soitec, of course, work on future generations of RF-SOI substrates continues unabated. You can be sure they’ve got a product roadmap focused on continued innovation and cost effectiveness for future mobile communication markets.
But in addition to working on its RF-SOI roadmap internally, Soitec is leading an international program to further develop the technology in collaboration with 16 partners from five European countries, representing the entire electronics value chain from raw materials to finished communication products. The REFERENCE Project, awarded in a call for projects by the Electronic Components and Systems for European Leadership (ECSEL) group ─ aims to create a European competitive industrial ecosystem based on RF-SOI.
Over the next three years, the REFERENCE Project expects to innovate new materials, engineered substrates, processes, design, metrology and system integration that pave the way for 5G wireless communications. The R&D and demonstration objectives for 4G+/5G technologies include Soitec’s development of RF-SOI substrates, and the production of RF-SOI devices at two major European semiconductor foundries. These advances will contribute to RF-SOI’s growing use in three targeted applications: cellular communications/the Internet of Things (IoT), automotive and aeronautics , including pioneering new frequency bands.
“Soitec is at the forefront of European innovation and we are very happy to be part of this very important European research project involving key partners beyond our direct customers,” said Nelly Kernevez, partnership director at Soitec. “This initiative allows us to build the European Union’s RF community, consolidate our vision of what the future can be, and leverage proven material technology to create RF communication solutions for tomorrow.”
The wireless world will keep progressing by leaps and bounds over the next few years. And it’s looking like ever-advancing RF-SOI substrates will be the springboard. Stay tuned!
RF-SOI substrate guru Jean-Pierre Raskin, whose team at UCL* has driven the technology behind the most advanced wafer substrates for RF applications, has been awarded one of the highest honors in electronics: the prestigious Blondel Medal. The technology he pioneered is now in virtually all the world’s smartphones, and used by just about every RF foundry on the planet.
Dr. Raskin’s team first demonstrated a radical new approach (dubbed “trap rich” at the time) for improving the RF performance of high-resistivity (HR) SOI substrates back in 2003. Teams from UCL and Soitec then worked together on the industrialization, making it commercially available in SOI substrates for RF applications.
ASN readers will recognize this work from a 2013 article Dr. Raskin co-authored, Soitec and UCL Boost the RF Performance of SOI Substrates.
The result was a new wafer substrate Soitec named eSI, for enhanced Signal Integrity, and it’s been wildly successful. In fact Soitec estimates that more than one billion RF devices are produced each quarter using their eSI wafers. It’s been used for 2G, 3G and now 4G and LTE. With the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), the latest iterations of the Raskin team’s technology are in Soitec’s most advanced eSI90 wafers.
The Blondel Medal is the highest honor awarded by the SEE (the French Society for Electricity, Electronics, IT and Communications Technologies). It recognizes a researcher under 45 years old who has authored works or recorded exceptional achievements that have contributed to the advancement of science in Information and Communication Technology.
*UCL is the Université catholique de Louvain in Belgium. Click here to read more about Dr. Raskin’s research group.
Soitec estimates that it has shipped enough of its eSI wafers to fabricate more than 1.4 billion RF front-end semiconductor devices. (Read the press release here.) The proprietary Enhanced Signal Integrity™ (eSI) substrates are now the substrate of choice for manufacturing cost-effective and high-performance radio-frequency (RF) devices providing a power boost for 4G /LTE applications.
For eSI, Soitec and the Université catholique de Louvain (UCL) developed a technique that adds a “trap-rich” layer underneath the buried oxide, which freezes the parasitic surface conduction that’s inherent in any oxidized silicon substrate. (The technical details are clearly explained in an excellent ASN post by the Soitec and UCL team leaders – click here to read it.) Using a set of very specific patents, Soitec applied proprietary technology and accumulated knowledge to build the new eSI product line.
This substrate provides a raft of advantages to RF design. Because the trap-rich layer is built into the substrate, it reduces the number of process steps and relaxes design rules, leading to a highly competitive performance and die cost, including a smaller area per function. RF designers can therefore integrate diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss, better thermal conductivity and better signal integrity than other technologies. (Click here to read Soitec’s ASN post from December 2013 describing all the RF design challenges eSI answers.)
Soitec has issued a highly-informative new white paper on its enhanced signal integrity – aka eSI™ – wafers for 4G and LTE/A applications (to get the paper, click here). Entitled “Innovative RF-SOI Wafers for Wireless Applications”, the paper explains the various challenges faced by RF IC designers, and how the new eSI wafers offer powerful solutions. The substrates on which devices for LTE apps are manufactured play a major role in achieving requisite levels of performance. They allow RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies. As described recently in ASN (click here), the new eSI wafers are now in high-volume production, and are being used at most of the leading RF foundries.
Soitec has reached high-volume manufacturing of our new Enhanced Signal Integrity™ (eSI) substrates, enabling cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production, and are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications.
This is a major addition to our Wave SOI™ family of high-resistivity (HR) wafers for wireless applications. Our HR-SOI wafers have been used by market leaders for almost a decade, successfully addressing the challenges of 2G and 3G networks. But the data transfer rates of the new generation of 4G and LTE protocols called for a new substrate solution that would help designers meet the higher linearity and increased integration requirements.
Working together, Soitec and Université catholique de Louvain (UCL) developed a technique that adds a “trap-rich” layer underneath the buried oxide, which freezes the parasitic surface conduction that’s inherent in any oxidized silicon substrate. (The technical details are explained in a related post – click here to read it.) Using a set of very specific patents, Soitec applied proprietary technology and accumulated knowledge to build the new eSI product line.
Because this layer is built at the substrate level, expensive process steps such as high-energy implant and conservative design rules are not required when designing on eSI wafers. The result is a cheaper process and potentially smaller die area per function.
The eSI substrate allows RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies.
Here is a table outlining some of the major performance advances in front-end module integration that the eSI substrate enables:
The adoption of RF-SOI wafers for RF switches in handsets is now over 65 percent (Source: Yole Développement). The first RF-SOI power amplifiers and integrated front-end modules are being well received and gaining momentum in the market. Based on current levels of adoption and performance, increasing use of RF-SOI wafers for integrated front-end modules is expected to follow the same adoption rate as seen with switches.
Looking back over the mobile revolution, we have seen the ever-increasing pressure on smart phone and device manufacturers to support increased demand for data traffic. Moving forward requires the contributions of all players along the value chain, including substrate manufacturers.
SOI substrates are playing a major role in RF applications. Soitec’s eSI product, developed and fine tuned over the past few years, is now qualified by several key customers and is already being used in volume production of mobile handsets on today’s market. Together, we are enabling the cost-effective integration of more and more functions as well as higher data throughput, smaller size, better reliability, improved performance and lower system cost.
NOTE: This article was largely excerpted from a white paper entitled Innovative RF-SOI Wafers for Wireless Applications. To download the complete white paper, click here.