To date, over 40 readers have commented on Handel Jones’ (IBS) EETimes post entitled FinFETs Not the Best Silicon Road (read post here). He noted that, “…next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today’s 28nm bulk HKMG CMOS…”. He then went on to say, “One option […] is fully depleted silicon-on-insulator (FD SOI). It gives lower cost per gate and lower leakage than bulk CMOS and FinFETs.”
Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here).
The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS & sensors), and the SOI manufacturing ecosystem.
The 1st day panel discussion was so interesting we’ll give it a post of its own, then follow up with round-ups of the presentations from both days.
The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF’s CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019.
VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI.
ST Director John Carey noted that ST’s been using FD-SOI since 2014. They’ve fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they’ve got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT.
The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it’s in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded.
Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung’s Lee said they’ve already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST’s Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained.
With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing.
The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung’s seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons.
Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that’s what tier-one players want.
Carey brought it back to RF-SOI (noting that ST’s introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won’t be the bottleneck he said, so what’s the FD-SOI/mmWave roadmap? Kengeri responded that GF’s ready. Lee said Samsung is also ready, and you’d see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it’s qualified. Carey said ST sees it first in consumer premises equipment that’s connected by satellite.
Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn’t give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it’s very important.
In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.
The presentations from the SOI Consortium sponsored workshop held during Semicon West are now posted and freely available on the website – click here to see the full agenda with links to the presentations. The workshop, entitled 4G/5G Connectivity: Opportunities for the SOI Supply Chain, was well-attended and generated excellent discussions.
If you don’t have time to look at all of the ppts, here are quick overviews.
Handel Jones is an industry veteran, China expert and longtime follower of the SOI ecosystem. High performance with low power consumption are the key requirements for the continued growth in the semiconductor industry, he said, making FD-SOI the right choice for a wide range of products. Here’s how he sees it:
He estimates the yearly TAM (total available market) for FD-SOI based products in the range of $46 billion over the next 10 years, largely driven by needs for ultra-low power and RF integration. He goes on to break out volumes by applications (including ISPs – image signal processors; and CIS – CMOS image sensors), foundry markets by feature dimension and to map out technology trends.
Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, Vice President, Globalfoundries.
Peter Rabbeni is an RF expert par excellence, having overseen the shipping of over 35 billion RF-SOI products to date. In his presentation, he details how 5G NR (New Radio) sub-6GHz frequency band specifications significantly increase frequency range and channel bandwidth, and how new band support and MIMO complexity and die size per handset are driving complexity in RF FEMs. Furthermore, 5G/mmWave phased arrays are driving a paradigm shift in the approaches that can be taken, he explains, so greater integration is needed. Here’s a great slide showing where GF’s two main SOI technologies come into play:
Working in partnership with industry leaders around the world, Leti has been the research powerhouse behind all things SOI since the early 1980s. In fact Reuters ranks them #2 in their most recent list of the World’s Most Innovative Research Institutions. This presentation reviews the key technical benefits of FD-SOI for IoT and IMT (that’s international mobile communications, btw).
This presentation really puts the context around engineered substrates. Here are two excellent and useful slides here that identify which engineered substrates go where in the 5G world, and the engineered substrates that Soitec provides. Check these out:
Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH.
In case you’re not familiar with them, Unity provides a wide range of solutions in metrology and inspection. Both the top silicon layer and BOX layer of wafers for FD-SOI applications have draconian requirements that have required new approaches in metrology to ensure the thickness and homegeneity control of these very thin layers.
Shanghai-based Simgui partners with Soitec, using SmartCut™ technology for the production of RF-SOI wafers. It is doubling its capacity to reach 400K over the next year, and expanding into 300mm. China is aggressively working on 5G and plans to deploy 5G commercialization in 2020. Jeff Wang’s is a terrific presentation detailing the rollout. (BTW, in addition to the massive funding effort underway, the government created the National Silicon Industry Group (NSIG) to support the semiconductor material ecosystem in China. You’ll want to keep up with what’s going on here). Here’s the slide that summarizes the SOI ecosystem in China – the presentation then goes on to detail who does what.
Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor.
K-T has played a strategic role in the SOI story going back for decades (and in fact they wrote a piece for the third edition of ASN back in 2005!), ensuring metrology innovations for things that hadn’t previously need detection and measurement. With each new set of requirements, they rose to the occasion with wafer metrology solutions that helped increase quality and decrease costs. This presentation recaps some of them.
The Chinese microelectronics ecosystem as well as leading companies worldwide have been meeting again for the sixth time in Shanghai at the Shangri-La Hotel during two days and exchanged on FD-SOI and RF-SOI technologies and applications.
FD-SOI FORUM AGENDA – SEPTEMBER 18
>Mass production and recent achievements of FD-SOI, Gitae Jeong, SVP, Samsung Electronics, (presentation not available)
>Driving Differentiated Solutions with FD-SOI for Demanding Markets, Thomas Morgenstern, SVP & GM, Fab 1, GlobalFoundries
>FinFET and FD-SOI: Market and Cost Analysis, Handel Jones, CEO, IBS
Deployment of FD-SOI: AIoT and Automotive Electronics, Wayne Dai, Chairman, President and CEO, VeriSilicon
Battery Powered Security and Monitoring Cameras for Smart Home, Yantao Jia, Head of ASIC & China Operations, Amazon/Blink (presentation not available)
>I-fuse ™ for FD-SOI: ultra-high reliability and ultra-low power OTP, Shine Chung, Chairman, Attopsemi
>Addressing the Energy Efficiency Challenges of IoT End Points, Frederic Renoux, EVP, Dolphin Integration
FD-SOI for Automotive: acceleration through ecosystem partnerships, Carlos Mazure, Chairman & Executive Director, SOI Industry Consortium
>L-4 Autonomous Solution based on 22FDX, Jiong Zhu, Director, Design Implementation, VeriSilicon
>Future applications yc AI with FD-SOI, Emmanuel Sabonnadière, CEO, LETI-CEA Tech
The second day was dedicated entirely to 5G connectivity and its infrastructure showcasing end users, fabless and the supply chain. For both days the program featured timely keynotes and in-depth panels discussing the hottest topics.
RF-SOI WORKSHOP AGENDA – SEPTEMBER 18
>Join Hands with Industry Partners – Hop on the 5G Shuttle Together, Danni Song, Project Manager, China Mobile
Riding the 5G Silicon Wave: How Advances in 5G Radio Architectures Benefit from RF-SOI , Michael Reiha, Head of RFIC R&D, Nokia Mobile Networks
>RFSOI Enabling the RF Wireless Front End : History, Future and Challenges Julio Costa, Director of Technology Development, Qorvo
>Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, VP Segment Offering Management, Business Development and Marketing, GlobalFoundries
>Engineered Substrates – At the Heart of 5G Connectivity, Thomas Piliszczuk, EVP, Soitec
RFSOI and Extended Silicon-Based Solutions: Prospectus for 5G Front-End Components and System Integration, Herb Huang, CEO, NSI
HHGrace 0.13um RFSOI: Enabling Integration of RFFE for 5G, Ruofan Dai, Senior Engineer, HHGrace (presentation not available)
>RF-SOI in 5G Era, Yangyang Peng, Director, SmarterMicro
>Sub-5G RF Front-End Components Based on Advanced SOI CMOS Process, Wayne Ni, CTO and Board Chairman, CanaanTek
>RF-SOI for RFFE Solution: An EDA Perspective, Feng Ling, Founder and CEO, Xpeedic
>Engineered Substrates: At the Heart of 4G/5G Front End Module Evolution, Bernard Aspar, EVP & GM, Soitec
>RF and SOI Technologies for 5G Deployment, Kirk Ouellette, VP of World Wide Strategy, STMicroelectronics
>RF Technology and Design Enablement for Next Generations, Mostafa Eman, CEO, Incize
>Applied Materials 300mm FEOL Products Status for RF-SOI, Papo Chen, Sr. Product Manager, Applied Materials
>Introduction to the Virtuoso RF Solution for Co-Design of RF Chips and Modules, Liang, Jiang, Principal Customer Engagement Engineer, Cadence
These two events were co-organized by
SOI technology is at the base of cellular wireless connectivity: 4G and 5G are driving up the demand for both 300mm and 200mm capacity, both in short supply. The 4G expansion and the introduction of 5G are also enlarging the scope to new applications and new frequency ranges, up to supporting mm-wave. The demand is not only about supporting continuously growing volumes, but requires to develop solutions using differentiated silicon technologies (RF-SOI, PD-SOI, FD-SOI) and to offer integrated system solutions (in-package modules, including integrated antennas).
The workshop has develop such requirements and the current solutions available from a supply chain perspective, involving substrate suppliers, equipment and material suppliers (for both substrate/silicon manufacturing and packaging solutions), and foundries.
Enabling the Engineered SOI Wafer, Sesh Ramaswami, Managing Director, Applied Materials (presentation not available)
Synergies with the SOI Industry, Olivier Vatel, Corporate Director, Senior Vice President and CTO of SCREEN Semiconductor Solutions, Screen (presentation not available)
Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH
Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor
The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.
These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.
Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:
Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.
“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.
The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.
FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.
This 5th Shanghai FD-SOI Forum was focused on IoT, Ultra Low Power pervasive computing, smart driving, mixed signal, and RF.
Winning with SOI, Dr. Sanjay Jha, CEO of Globalfoundries
Cutting-edge Technology from a Trusted Foundry, Dr. ES Jung, EVP & GM of Samsung Foundry
Advancement in Edge Computing with HMI Interfaces, Artificial Intelligence and FD-SOI, Ron Martino, VP & GM of NXP
>FD-SOI Opportunities in Deep Learning and Artificial Intelligence Applications, Dr. Handel Jones, CEO of IBS
NSIG Support of SOI Ecosystem, Nabeel Gareeb, CEO of NSIG
Accelerating SOI Mass Adoption, Paul Boudre, CEO of Soitec
Benefits of 22FDX for NB-IOT RF Integration, Tom McKay, Director, RF Innovation, RF Pathfinding – Santa Clara, Globalfoundries
>Energy Efficient RISC-V Processor Design Using 28 FDS, Borivoje Nikolic, Professor of UC Berkeley
>SoC Product Design with Body Biasing Using FD-SOI, Jiong Zhu, Director of VeriSilicon
> From Concept to Mass Production, Qi Wang, VP of Cadence
>Design with FD-SOI, Innovation through Collaboration, Swami Venkat, Director of Synopsys
ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.
The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.
Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.
If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.
CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.
FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF. ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).
The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption. Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.
In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.
Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)
NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing. A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP) is heading to new levels, he says.
With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.
Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)
Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.
Briefly, here are some more highlights.
Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings. But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.
Dreamchip: Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI. One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection. They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB). The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.
Greenwaves: CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros. The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.
Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.
IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim. FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.
The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp. IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled: lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.
All in all, it was another really good day for FD-SOI in Silicon Valley.
Technology Application In Embedded Processing – GEOFF LEES, SVP & GM, Microcontrollers, NXP
Low Power IP: Essential Ingredients for IoT Opportunities – RON MOORE, VP, Physical Design Group, ARM
Growth Areas for IOT and Impact on FDSOI – HANDEL JONES, CEO, IBS
FD-SOI in a Connected World – JOHN KOETER, VP, Marketing Solutions Group, Synopsys
IoT Unique Identity Overlooked – MAURIZIO PAGANINI, CMO, Megachips
A New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI – JENS BENNDORF, COO, Dreamchip
Enabling the Smart IoT – LOIC LIETAR, CEO, Greenwaves
FDSOI Factors of Success Pave New Roadmaps – MARIE-NOELLE SEMERIA, CEO, Leti, Institut de CEATech
The panel discussion rounding out the day at the recent FD-SOI Forum in Shanghai ended an exciting week (GF’s 12nm FD-SOI & ecosys, Sony’s FD-SOI GPS in the Huami watch) on a decidedly optimistic note. Here’s a quick rundown of some of what was said.
(As soon as the presentations given earlier in the day are posted, we’ll take a quick cruise through those, too.)
Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits started it off with the reminder that for anything “always on” in IoT, FD-SOI’s always better. They had a terrific experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt here). The port from 28 bulk took 2 1/2 months (vs. to FinFET, which took almost 6). Even without using body bias, they got performance up by around 15% and leakage down by about 30% (he added that with body bias, they could get five times that).
He compared porting to FD-SOI to playing high school ball, vs. a port to FinFET which is like competing in the Olympics. ESD was different, but not a big deal – you just need to “read the manual”. Heating? Nothing an engineer can’t resolve. For IoT, FinFETs are like using a cannon to shoot a mosquito, he quipped.
He later ticked off a few more advantages of FD-SOI for the IoT design community: system cost, lower power – and here’s a particularly interesting observation – cheaper packaging. They were able to do wire bonding, so they were able to package a wearable video app in a plastic capsule. All things considered, FD-SOI offers the perfect solution, he said (and now he’s got silicon with “dramatic results” to prove it), adding that the IP guys need to evangelize this.
GloFo VP Subramani Kengeri took a moment to look back before he looked forward. “FD-SOI is not new,” he reminded us. It was explored and researched for a decade. But at the beginning, CPUs were driving the industry, and everyone else followed suite. But now in mobile and IoT, RF is becoming more important, and what was good for the CPU is no longer what’s good for everything else. He tipped his hat to Soitec, ST and Leti, who “kept the lights on” and kept driving FD-SOI forward. Now with 5G on the horizon, FD-SOI is the enabler, he added.
He also noted that FD-SOI gets you the maximum memory onchip, and that with 12FDX, we’ll be seeing the world’s smallest SRAM. So that opens a new degree of freedom. The EDA partners have been working on automating body bias in the PDK for greater power management. He cites an ARM core with on-demand performance that can be used “intelligently”. Is it complicated? Not really, he says, especially if it’s automated. In fact he sees body bias opening the market for “extraordinary, innovative products” very soon. Key IP is in place. And it’s not just for IoT: aside from high-end CPUs, FD-SOI is optimal for everything. “Everything’s happening now, and it’s moving really fast,” he said.
SOI wafer leader Soitec VP Christophe Maleville was asked if he saw any limit on manufacturing the ultra-thin wafers for the 7nm node. No problem, he said – they can do those wafers with 4nm of strained top silicon and a 10nm layer of insulating BOX. They’ve been working on FD-SOI wafers for over a decade, he reminded us, with Leti, IBM and ST. Back in 2013 when ST announced the Nova-Thor hitting 3GHz (or 1GHz at just 0.6V), everything was in place: the metrology was ready, reliability was controlled.
Today they’ve got a 15nm BOX layer in manufacturing, with no limits in moving to 10nm for customers going for very low power. For the strained top silicon needed for the 7nm node, they spent years working on strain with IBM et al in Albany, so they’re not starting from scratch. That substrate will be mature in just two years, so from a substrate point of view, he said, “7nm is no problem”.
In response to a follow-up question from a well-known analyst in the China tech industry, panel moderator and Verisilicon CEO Wayne Dai said that the design community in China has the skills to do FD-SOI, no problem. He’d like to see more IP, but FD-SOI has powerful advantages in terms of cost, analog/memory and back biasing.
Dai then asked the panelists if they thought we’d be seeing a foundry in China opting for FD-SOI by next year – all but one said yes. One thing all the panelists agreed on, however: they all expect to see FD-SOI products (and lots of them) on the stage at the Shanghai FD-SOI forum in 2017.