Gold Standard Simulations Ltd. (GSS) announced a multimillion dollar contract to license its complete TCAD/EDA tool suite to GlobalFoundries (see press release here). The fully integrated and automated tool chain includes GARAND, the GSS ‘atomistic’ TCAD simulator; Mystic, the GSS statistical compact model extractor; and RandomSpice, the GSS statistical circuit simulator. The GSS tool suite is the world’s only fully integrated tool chain that performs simulation-based Design/Technology Co-Optimisation (DTCO) in advanced bulk, FD-SOI and FinFET technologies, including statistical variability and reliability.
“At 14nm FD-SOI is much cheaper, 30-40% cheaper, than Intel’s technology,” Asen Asenov told David Manners in a recent Electronics Weekly post (see full post here). Asenov is CEO and Founder of Gold Standard Simulations (GSS). The subject of the post was how TSMC has turned to GSS for statistical analysis tools. Professor Asenov is a fan of ST’s FD-SOI, noted Manners. The main challenge is building the ecosystem, he concluded.
Following investigations and simulations, GSS has declared, “Metal-gate-first FD-SOI will be very good but metal-gate-last could be spectacular.” “…the technologist who that could develop and deliver metal-gate-last FD-SOI at 28nm will be able to offer you supply voltage below 0.5V,” they explained. They also noted, “The statistical variability introduced by the random discrete dopants in the FD-SOI MOSFETs is significantly lower compared to bulk MOSFETs with equivalent dimensions.”
Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere. But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.
GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks. The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones. Then they also need to provide reliable models to designers who will use them before committing chips to silicon. One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs. This covered “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”. Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project. It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
A few months later, when Chipworks published pictures of the (bulk silicon) Intel 22nm FinFETs, the folks at GSS started a series of blogs that caught the attention of major tech pubs such as EE Times, Electronics Weekly and EDN. For reference, here are the blogs and basically what they concluded:
Specifically, the July 27th blog indicated that if FinFETs are rectangular in shape, drive current would be 12-15% better. Would that be easier to do on an SOI wafer? Soitec has argued that their “fin-first” SOI-based approach to FinFET manufacturing will save both time & money while getting better results (see Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET in Semiconductor Manufacturing & Design).
The GSS blog also reminded readers that the company’s CEO and founder, Asen Asenov (an extremely heavy hitter who’s published over 550 papers), has hinted that “…SOI FinFETs with an almost ideal rectangular shape may be a better solution for future FinFET scaling”. GSS has noted previously that “FinFETs built on an SOI substrate could have significant advantages terms of simpler processing, better process control and reduced statistical variability”.
Fin shape aside, GSS said that by virtue of the layer of insulation, SOI would give another 5% boost to FinFET drive current. But perhaps more importantly, that layer of insulation in SOI-based FinFETs would deliver on average 2.5 times less leakage – which would translate into a doubling of battery-life for your cell phone.
IBM has now entered into an agreement with GSS et al on a project called StatDES, for Statistical Design and Verification of Analogue Systems – see last month’s IBM blog by IBM Research Scientist Dr. Sani Nassif, entitled “Fins on transistors change processor power and performance”.
Dr. Nassif writes, “IBM, University of Glasgow and the Scottish Funding Council are collaborating on a project to simulate 3D microprocessor transistors at a mere 14 nanometer scale (the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator (SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES, promises to keep improving microprocessor performance and energy conservation.”
The steering group also includes folks from ST, Freescale, Wolfson and Cadence, so one would guess we’ll be hearing more from this project – and others like it, to be sure – in the future, wouldn’t you think?
> Digital Business Transformation – Why IOT is changing everything? By Aglaia Kong, CTO/VP, IOT Solution, Cisco Systems
> Enabling the Digital Connected World with FDSOI by Thinh Tran, President & CEO, Sigma Designs
> Smart Technology Choices and Leadership Application Processors by Ron Martino, Vice President, Application Processors Product Line, NXP Semiconductors
> Enabling Next Generation Semiconductor Product Innovations with 22FDX™ by Subramani Kengeri, VP CMOS Business Unit, GLOBALFOUNDRIES
> Realize the potential of FDSOI by Will Abbey, General Manager, Physical Design Group, ARM
> 28FDS – Industry’s first mass produced FDSOI technology for IoT era, with single platform benefits by Kelvin Low, Senior Director, Foundry Marketing, Samsung Semiconductor Inc (SSI)
> Low Power GPS design with RF circuit by the FDSOI 28nm by Kenichi Nakano, Senior Manager, Section8 System Analog Product Department, Analog LSI Business Division, Device Solution Business Group, Sony Semiconductor Corporation
> FD SOI: Disruptive or Just Another Process? by Dan Hutcheson, CEO and Chairman, VLSI Research
> A Case Study of Half Power SERDES in FDSOI by Mahesh Tirupattur, EVP, Analog Bits
> Synopsys 28FDSOI Solutions by Mike McAweeney, VP IP Product Sales, Synopsys
> High-speed optical communication ASIC: FDSOI promise and reality by Naim Ben-Hamida, Senior Manager, Ciena
> Cadence FD-SOI Implementation Solution by Rod Metcalfe, Group Director, Digital and Signoff Business Group, Cadence
> Mixed-Signal Design Innovations in FDSOI Technology by Boris Murmann, Professor of Electrical Engineering, Stanford University
> Communication Infrastructure Disruptions Caused by the Forthcoming IoT Data Deluge: the FD-SOI Solution by Simon Callewaert, Sr. Manager Digital/Mixed Signal ASICs Marketing, STMicroelectronics
> FD-SOI Power Optimization Challenges by Ali Erdengiz, Business Developer, CEA-LETI
> Silicon Impulse: Your gateway to FD-SOI success by CEA-Leti
> FD-SOI power optimization flow by CEA-Leti
> Impact of Backplane Configuration on the Statistical Variability in 22nm FDSOI CMOS by Gold Standard Simulations (GSS) & GLOBALFOUNDRIES
> Wafer Supplier Aspects of FD-SOI and RF-SOI by Shin-Etsu Handotai
The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.
To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.
08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM – 10:50AM – Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium
Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:
Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA
If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.
> Opening Keynote by Babu Mandava, CEO, Ineda Systems
> Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era by Shiro Kamohara, Chief Professional, Renesas Electronics Corp.
> Enabling SoC Innovations with 22FDXTM by Subramani Kengeri, VP of Global Design Solutions, GlobalFoundries
> The industry’s first mass-produced FDSOI technology for the IoT era, with single design platform benefits by Yongjoo Jeon, Principal Engineer in SEC Foundry marketing, Samsung
> FD-SOI In The Connected World by Navraj Nandra, Sr. Director, IP Product Sales, Synopsys
> FDSOI Technology Advantages for Analog/RF and Mixed-Signal Designs by Andreia Cathelin, Senior Member of Technical Staff, STMicroelectronics – ST FD-SOI Technology
> Expanding FD-SOI Design and Application Options by Shirley Jin, Sr. Director of Engineering, Verisilicon
> Paradigm Shift from Standard Cell design methodology to the Platform ASIC Design methodology with SOI by Seiji Miwa, President Japan, Baysand
> Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms by Christophe Maleville, Senior Vice President, Digital Electronics BU, Soitec
> Introduction on VDEC activities and FD-SOI Chip Fabrication Services by Makoto Ikeda, Professor, VDEC, University of Tokyo
> 300mm RFSOI Development toward IoT Era by Kenji Tateiwa, General Manager of R&D Strategic Planning, TPSCo
> RFSOI: Defining the RF-Digital Boundary for 5G by Peter Rabbeni, Sr. Director RF Product Marketing and Business Development, GlobalFoundries
> Tunable FEM Integration and Architecture Innovation in RF SOI CMOS by Barend van Liempd, PhD Researcher, imec and Vrije Universiteit Brussels
> SOI Needs Better than IR-Drop by François Clément, CTO, CWSEDA
> ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration by Pietro Maestri, RF Product Line Director, STMicroelectronics
> LAPIS’s SOI Sensor Technology by Masao Okihara, Sensor Development Group, Device Technology Development Division, Lapis
> MEMS&NEMS at the heart of More than Moore: technologies and integration overview by Yann Lamy, Program Manager, CEA-Leti
> SOI based Image Sensors Using Backgate Pinning Techniques for Soft X-ray, Near Infrared and Time-of-flight Range Imaging by Shoji Kawahito, Professor, Research Institute of Electronics, Shizuoka University / Chairman CTO, Brookman Technology Inc.
> 100G Optical Communication using ST Silicon Photonics Products by Kirk Ouellette, Director Digital Product Group, STMicroelectronics
> Silicon Photonics Technology on SOI wafers for Optical Interconnect by Tohru Mogami, Chief Manager, PETRA
> Impact of Backplane Configuration on the Statistical Variability in 22nm FDSOI CMOS by Gold Standard Simulations (GSS) & GlobalFoundries
> Advanced Technology Entablement for RF SOI by Incize
> Wafer Supplier Aspects of FD-SOI and RF-SOI by Shin-Etsu Handotai
> Soitec, your innovation partner by Soitec
> When Power is Paramount by SureCore
April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosystem.
Wow, were we precient.
Consider some of the topics we covered in that first edition, back in April of 2005:
FinFET on SOI (that was at 45nm)
NXP (then Philips) massive use of SOI for automotive chips (they were already running 3 million SOI-based transceivers a week back then)
a piece on low-power design with SOI by Jean-Luc Pelloie, who’s now an ARM Fellow and the company’s Director of SOI Technology
Intel had just published their first photonics on SOI papers in Nature (and yes, their photonics program is absolutely still on SOI)
ASN was recently invited to give a talk about SOI-based applications at the Shanghai Academy of Sciences (SIMIT). Putting together a presentation of SOI-based apps from the last decade turned out to be a lot of fun – and a real eye opener.
The presentation is now posted on SlideShare (click here to see it).
It reminded me that we have a veritable treasure trove of information here, both current and historical. We count contributions from virtually every major player in the industry.
If you haven’t done so recently, I’d like to invite you to explore the ASN website. With a decade’s worth of articles, that might seem a little daunting. But on the right, you’ll see our list of Tags – if you click on “All Tags” you’ll get an alphabetical listing of every topic you could think of.
We’ve come a really long way in this decade. When Oki did their FD-SOI chip for Casio in 2005, they did it on a regular SOI wafer, and it was a breakthrough. Then the announcement by Soitec in 2010 that the company had entered industrial production of the ultra-thin SOI wafers needed for high-volume FD-SOI apps opened up a whole new horizon. (Remember that until that point, nobody believed it would be possible to produce SOI wafers with the requisite top silicon uniformity of +/- 5 Angstroms.)
Now that the ecosystem’s in place, solving the low-power/high-performance challenges of IoT cost effectively, we’re all anxiously awaiting the end of this year for announcements of those high-volume FD-SOI apps.
Consider where we are today. ST says they have 18 FD-SOI design wins as of January 2015. Synapse Design has worked on 7 projects and sees more coming in. Verisilicon has some in the pipeline. GlobalFoundries has indicated they have customers lined up. And of course with the big news last year that Samsung is offering FD-SOI on a foundry basis, they are firmly behind it. Foundries mean business. If they’re offering it, it’s because they have customers.
And then there’s the RF-SOI – what an immense success. Partners Soitec and UCL had been quietly working for years on an innovative eSI substrate solution that would solve the challenges of 4G and 5G. Then suddenly it was in every new smartphone out there, and the next-gen wafer can actually predict 5G performance.
In other SOI strongholds, things are looking very good, too. Currently there are about 800 chips per vehicle – that number is on track to reach 1000 by 2020. In smart power, SOI wafers made using Soitec’s Smart Cut technology are seeing 20% CAGR, compared to 7% for the rest of the industry.
So if you want to share our crystal ball, keep reading ASN. Join our mailing list, follow us on Twitter @followASN, join our Advanced Substrate News LinkedIn group, and look for us we gear up as AllThingsSOI on WeChat.
The beginning of 2015 has been outstanding. We’ve seen double even triple the hits to the ASN website in recent months, so people are clearly looking to learn more about SOI.
I’d like to take a moment to thank the folks at SOI-wafer leader Soitec. They have sponsored ASN since day one. And thank you, too, to all the members of the SOI Consortium, who’ve given generously of their time with unflinching support and keen insights.
In the decade since ASN’s creation, we’ve seen an ecosystem blossom. Here’s to the next decade, and the new era of high-volume, low-power, high-performance SOI-based chips.
With warm regards,
Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array control and sensing scheme, which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models, sureCore has designed an SRAM memory consuming less than half the power of existing solutions. SureCore is working closely with Gold Standard Simulations (GSS) Ltd. (GSS Founder/CEO Asen Asenov is a sureCore director).